1. Field of the Invention
The present invention relates to a memory/logic conjugate system.
2. Description of a Related Art
In recent years, the complicated architecture of a CPU has been limiting improvement of its performance in comparison with the many number of circuits therein. In addition, the circuits have low flexibility which prevents dynamic reconfiguration according to applications. This may cause the fatal problem of system crashes and therefore a more flexible and robust system is required. FPGA (FIELD PROGRAMMABLE GATE ARRAY) has been playing a part thereof. It can be reconfigured in the field. Although multi-core systems with a collection of simple cores have also been proposed and drawn attentions as a dynamically reconfigurable architecture, their development seems to be limited because a bandwidth bottleneck (bottleneck of the number of wirings) occurs when a crossbar switch is used to cope with an increase in scale. A circuit referred to as a memory, i.e. logic that can save the number of wirings, may be a solution. However, it does not provide a solution because the crossbar switch cannot be omitted for random access between memory mats each including a plurality of memory cells, and the crossbar switch itself is a memory circuit, thus using a large amount of memory.